Browse Prior Art Database

Chip Bussing to Enhance Tab Peformance

IP.com Disclosure Number: IPCOM000037795D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Greer, SE: AUTHOR

Abstract

Busses are formed by deposition masking or lift-off processing while forming normal connector bumps on semiconductor chips. Large cross-section metal busses reduce wiring resistance, thus improving performance of tab connected circuits.

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Chip Bussing to Enhance Tab Peformance

Busses are formed by deposition masking or lift-off processing while forming normal connector bumps on semiconductor chips. Large cross-section metal busses reduce wiring resistance, thus improving performance of tab connected circuits.

Referring to the figure, silicon chip 2 is a complete integrated circuit having a few tabs 4 bonded as usual to connecting bumps on the edge of the chip 2. Tab 6 is connected to voltage bus 8 and tab 10 is connected to ground bus 12. Decoupling capacitor 14 is connected between ground bus 12 and voltage bus 8. Voltage bus 8 makes contact to underlying circuitry through via holes 16 in insulation over connected lines. Ground bus 12 makes contact with appropriate underlying circuitry through via holes 18 in insulation over connected lines. Note that bus geometry can be designed to provide regions for tab connections which are devoid of underlying circuitry, thus the possibility of damage to circuitry by the tab connection process is minimized.

Ground bus 12 and voltage bus 8 are made with the same metallurgy and in the same process step which is used to create chip edge connecting bumps. Definition of bus and edge bump patterns is performed by any of several methods, e.g., deposition masking, lift-off processing, or photo etching, whichever is appropriate for the pattern shape and resolution required.

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