Browse Prior Art Database

Mimimum Area Floating Gate Tie-Down Structure

IP.com Disclosure Number: IPCOM000037796D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR [+2]

Abstract

A CMOS semiconductor structure is shown which utilizes existing technology features to implement a polysilicon-to-N+ or Pdiffusion contact in a minimal area.

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Mimimum Area Floating Gate Tie-Down Structure

A CMOS semiconductor structure is shown which utilizes existing technology features to implement a polysilicon-to-N+ or Pdiffusion contact in a minimal area.

A process ground rule requiring all polysilicon lines that form gates be contacted to a diffusion after the first level metal (M1) can be satisfied through the utilization of a structure shown in the figure. A polysilicon (PC) line partially intersecting an area above a diffusion is shown in the top view. A narrow rectangular contact area (CA) opening extends from over the PC line to the diffusion area below. A cross-section shows tungsten (W) fill metal in the contact area providing a tie-down structure from the polysilicon line (floating gate) to the diffusion.

The new structure provides the following advantages:

1. No additional process steps are required.

2. A smaller contact area is required than separate M1 contacts to polysilicon and diffusion. 3. No metal line is required above the contact, minimizing the impact to adjacent M1 wiring.

Disclosed anonymously.

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