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Browse Prior Art Database

Alignment Aid for Stud Up Technology

IP.com Disclosure Number: IPCOM000037799D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR

Abstract

A semiconductor alignment aid may be formed in a planar surface by placing a vertical metallurgical "stud up" structure generated in the normal process sequence in a large (non-functional) area. The resulting "artificial" valley created on the chip represents the deepest valley on the chip. In so doing, the etching of the studs and insulator result in exposing the stud mask in this area and the stud conductor everywhere else. By wet etching the stud mask preferential from the field and stud metal areas, a topographical alignment aid is created first order to the stud level.

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Alignment Aid for Stud Up Technology

A semiconductor alignment aid may be formed in a planar surface by placing a vertical metallurgical "stud up" structure generated in the normal process sequence in a large (non-functional) area. The resulting "artificial" valley created on the chip represents the deepest valley on the chip. In so doing, the etching of the studs and insulator result in exposing the stud mask in this area and the stud conductor everywhere else. By wet etching the stud mask preferential from the field and stud metal areas, a topographical alignment aid is created first order to the stud level.

This method may also be used to determine topographical depths post- planarization, in that only the deepest valleys will leave a stud mask. If the stud mask is composed of layers of different materials and thickness, levels between the stud conductor and the deepest valleys can be determined and highlighted.

Referring to the figure, the functional and non-functional areas of the chip are identified on either side of the dotted line.

Disclosed anonymously.

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