Browse Prior Art Database

Obtaining Chip Identification Via Self-Test

IP.com Disclosure Number: IPCOM000037836D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+4]

Abstract

This invention is a method of identifying a logical entity from a set of different logical entities. The logical entities may be different logic cards, different versions of a logic card, different chips, or any other fixed set of logical entities.

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Obtaining Chip Identification Via Self-Test

This invention is a method of identifying a logical entity from a set of different logical entities. The logical entities may be different logic cards, different versions of a logic card, different chips, or any other fixed set of logical entities.

The invention uses Random Pattern Self-Test. It applies a common set of pseudo-random patterns and compares the results of the patterns to a table of expected results. Expected results are predetermined for all versions of the logical entity; there must be a unique result for each version. The invention compares the signature collected for a particular entity against a table of good signatures for known levels of the entity, or a table of signatures of the different types of entity. If an entry in the table matches the signature, then the entity is the type indicated by that table entry.

This technique allows for identification of various levels of a card in a system with little overhead (no extra pins or logic in the logic whose level is to be determined).

In a computer system in which Random Pattern Self-Test is used to perform card (or subsystem) verification, the support system must know exactly the combination of chips that comprise any card (even if the chip variants are "functionally equivalent").

That is, the exact level of the card is important, even if microcode does not change between two levels of cards. Self-test is dependent on the exact logic structure of the chips, and small-chip changes that do not affect function will produce different results in random pattern self-test; the chip version must be determined so that appropriate self-test expected results can be selected.

Random Pattern Self-Test utilizes a linear feedback shift register called a Pseudo-Random Pattern Generator (PRPG) 1 (see figure) as a test pattern source. Bit streams are obtained from taps on the PRPG 2 and are scanned into the card to be verified...