Browse Prior Art Database

Technique to Determine Bounding Vector Locations for Module Static Idd Measurements

IP.com Disclosure Number: IPCOM000037861D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

McLean, JG: AUTHOR

Abstract

This article describes a technique which eliminates trial and error or guesswork in finding best and worst case vector pattern locations for module static supply current (Idd) testing that can be adapted to any tester or tester programming language.

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Technique to Determine Bounding Vector Locations for Module Static Idd Measurements

This article describes a technique which eliminates trial and error or guesswork in finding best and worst case vector pattern locations for module static supply current (Idd) testing that can be adapted to any tester or tester programming language.

Static Idd measurements are an important part of module testing. The results obtained during a static Idd test may vary significantly depending on the pattern conditioning (test vectors) applied to the module prior to the test. It is desirable to know the exact vector pattern locations which provide the worst-case (highest) and best-case (lowest) Idd measurements. The technique disclosed herein allows this determination to be made quickly and accurately, by exhaustively searching all possible vector locations in an automated fashion.

In addition to use in module testing the technique may be used in association with appropriate vector generation software to provide a defect screen for module technologies such as CMOS in which pattern-sensitive Idd changes may indicate latent defects.

The drawing is a flow chart of the technique disclosed herein.

Disclosed anonymously.

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