Browse Prior Art Database

Wiring Process

IP.com Disclosure Number: IPCOM000037912D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-30
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR

Abstract

The addition of an "MO" or preliminary metallization level immediately above the contact openings of circuit chip devices prior to depositing planarization insulation permits use of contact studs having smaller, uniform diameter and promotes greater wiring density on the planar insulation. This preliminary metal level can be used for local wiring and to prearrange the contacts to intersect planar wiring.

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Wiring Process

The addition of an "MO" or preliminary metallization level immediately above the contact openings of circuit chip devices prior to depositing planarization insulation permits use of contact studs having smaller, uniform diameter and promotes greater wiring density on the planar insulation. This preliminary metal level can be used for local wiring and to prearrange the contacts to intersect planar wiring.

In the figure, NPN transistor 1 and Schottky barrier diode 2 are illustrated. After the addition of p+ polysilicon layers 3, oxide layers 4 and n+ polysilicon layer 5 for the transistor, contact opening 6 is formed. Initial "MO" level metallization contacts 7 are then deposited in desired patterns to permit interconnecting studs 8 to be later formed through openings etched in planar insulation layer 9. After stud formation, the formal metallization pattern is then deposited, appropriately interconnecting with the studs. The initial metallization contacts can be readily formed by conventional means, such as sputtering, and then patterned, and the stud openings etched in layer 9. This early metal layer permits the stud location to be adapted to the formal interconnect wiring paths.

Disclosed anonymously.

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