Browse Prior Art Database

RAM Read/Write Controller During Self-Test

IP.com Disclosure Number: IPCOM000037935D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Doney, RM: AUTHOR [+2]

Abstract

This article describes a RAM read/write controller which provides a signal probability of 50% to be "1" or "0".

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 86% of the total text.

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RAM Read/Write Controller During Self-Test

This article describes a RAM read/write controller which provides a signal probability of 50% to be "1" or "0".

Traditionally, embedded arrays within a VLSI chip were tested by functional test patterns. That is, exercise read or write operation in special sequences such as walking ones, read after write, write after read. As the density of VLSI chip increases, on-chip built-in self-test (BIST) becomes an important technique. Most BIST techniques can test logic circuits very well. However, to test embedded array using random patterns is still a problem. Various methods were proposed to use additional logic such as address counter to perform some degree of self- test. In many cases, the amount of overheads and possible additional delays make the array self-test impossible.

Another method for self-testing an embedded array requires the following steps: 1. Modify the signal probability of array address lines to 0.5.

2. Modify the read/write circuitry to obtain a write probability of 0.5. 3. Modify the data input lines to obtain a signal probability of 0.5.

The sole figure shows a block diagram of the controller. Upon system reset, a zero is loaded into the register R through MUX M1. As long as the self-test input remains inactive, the feedback path will maintain the zero in the register. This initializes the register to a known (READ) state. MUX M2 will steer RAM WRITE lines (R-RAMWTR) as long as the self-test input remains...