Browse Prior Art Database

Tri-State Double Inverter Buffer

IP.com Disclosure Number: IPCOM000037946D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR

Abstract

This new tri-state complementary metal oxide silicon (CMOS) buffer circuit allows an open impedance state without the usual larger area, higher power consumption and greater complexity of previous circuits.

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Tri-State Double Inverter Buffer

This new tri-state complementary metal oxide silicon (CMOS) buffer circuit allows an open impedance state without the usual larger area, higher power consumption and greater complexity of previous circuits.

Referring to the figure, a split input inverter using transistors P1 and N6 results in driving output devices P3 and N8 to their off states directly. Transistors P2 and N7 are restore devices. Transistor P1 is used to turn off transistor P3 and also to turn on transistor N8 through transistor P4. Similarly, device N6 is used to turn off transistor N8 and also to turn on transistor P3 through device N5.

Because of the dual functions of transistors P1 and N6, this circuit uses fewer devices than usual. Thus, wiring, layout complexity, and area are reduced.

Disclosed anonymously.

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