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Design Methodology for Test Time Reduction in Dynamic Random-Access Memory

IP.com Disclosure Number: IPCOM000037948D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 7K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+8]

Abstract

Dynamic random-access memory (DRAM) test time is reduced by using an internal high-speed static random-access memory (SRAM) as an interface. SRAM positions normally addressed individually can be examined collectively by using an exclusive OR (XOR) circuit.

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Design Methodology for Test Time Reduction in Dynamic Random-Access Memory

Dynamic random-access memory (DRAM) test time is reduced by using an internal high-speed static random-access memory (SRAM) as an interface. SRAM positions normally addressed individually can be examined collectively by using an exclusive OR (XOR) circuit.

This procedure uses normal chip input/outputs (I/Os) for two functions during test read. First, to identify whether to expect a "1" or a "0" to be read out and second, to indicate to the tester the results of the XOR compare of previously written data.

Size of the SRAM bounds the potential test time advantage. A larger SRAM decreases test time because a larger number of cells can be tested in parallel.

This special test mode can be invoked without extra connections by use of an internal program load (IPL) feature. Therefore, this test can be done at both wafer and module test.

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