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Additive Process for Making Small Polysilicon Gates

IP.com Disclosure Number: IPCOM000037953D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bracchita, JA: AUTHOR [+2]

Abstract

An additive polysilicon definition process is used to create gate conductors of size smaller than photo limits allow. The process results in self-aligned source and drain contacts, the dimensions of which may also be below photo limits.

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Additive Process for Making Small Polysilicon Gates

An additive polysilicon definition process is used to create gate conductors of size smaller than photo limits allow. The process results in self-aligned source and drain contacts, the dimensions of which may also be below photo limits.

Referring to the figure, an oxide 2 is grown on silicon substrate 4. Silicon nitride (Si3N4) layer 6 and then oxide layer 8 are deposited next. An opening, having minimum photo width W, is defined and etched through oxide 8, stopping on nitride 6. Nitride is then conformally deposited and reactive ion etched, stopping on oxide 2, to leave sidewall spacers 10. Next, oxide 2 is removed from the opening by a wet etch. Gate oxide 12 is then grown. Polysilicon 14 is conformally deposited to completely fill the opening above the gate oxide and planarized to completely remove all polysilicon 14 on horizontal surfaces. The top surface of polysilicon 14 is then oxidized to form protective film 16.

Nitride 10 is etched and source and drain diffusions may be implanted either through the remaining oxide or the oxide may be removed first. Devices are completed by standard processing.

Disclosed anonymously.

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