Browse Prior Art Database

High Availability "N" Power Supply System

IP.com Disclosure Number: IPCOM000037977D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Hottenstein, D: AUTHOR [+4]

Abstract

In a so-called "N+1" system, at least one more power supply is provided than the load requires.

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High Availability "N" Power Supply System

In a so-called "N+1" system, at least one more power supply is provided than the load requires.

The load characteristic is such that current is proportional to clock speed in CMOS type load environments.

By adjusting clock speeds to decrease load power when a power supply failure occurs, high availability can be achieved without adding additional paralleled power supplies.

In operation, when a power supply failure occurs, the condition is signaled to a logic maintenance system, which degates the clock signal to all logic chips, resulting in an almost zero current condition for CMOS logic. The clock speed is decreased to a predetermined value, such that the current drawn by the load will not exceed the current available from "N-1" power supplies.

The system continues to operate in a degraded mode until the power supply can be replaced.

Disclosed anonymously.

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