Browse Prior Art Database

Early I/O Address Validation

IP.com Disclosure Number: IPCOM000038040D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

Disclosed is a method by which an I/O controller can validate I/O addresses before being received by the I/O device. This method increases system performance because the I/O controller can validate addresses faster than the slower I/O devices. (Image Omitted)

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Early I/O Address Validation

Disclosed is a method by which an I/O controller can validate I/O addresses before being received by the I/O device. This method increases system performance because the I/O controller can validate addresses faster than the slower I/O devices.

(Image Omitted)

The system processor communicates with the serial link adapters via an I/O controller that is attached to a high speed processor bus Fig. 1. When the processor executes I/O load or store instructions the address of the serial link adapter is first placed on the bus. Due to the pipelined nature of the processor the I/O address needs to be validated so that exception conditions can be matched with the exact instruction that failed. Since it would take many cycles to have a serial link adapter validate the address the I/O controller handles this checking.

The processor can handle many different I/O load and store formats, single words or multiple words up to 32 in length. All of the different formats must pass the validity checks. Checks are made to ensure all addresses are word aligned, that the address is within a valid range, certain addresses are rejected depending on the state of the serial link adapter, multiple word instructions must encompass a valid range and all addresses must be in a valid format. If the I/O controller detects an address that is invalid the processor is immediately notified. An exception can then be matched directly to the failing instruction. For address...