Browse Prior Art Database

Synchronizing State Machines Running on Different Frequency Clocks

IP.com Disclosure Number: IPCOM000038044D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+2]

Abstract

Disclosed is a method by which synchronous state machines operating on different frequency clocks can communicate their 'states' across the asynchronous boundary. This circuit guarantees that no ambiguous 'states' will be received.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 94% of the total text.

Page 1 of 1

Synchronizing State Machines Running on Different Frequency Clocks

Disclosed is a method by which synchronous state machines operating on different frequency clocks can communicate their 'states' across the asynchronous boundary. This circuit guarantees that no ambiguous 'states' will be received.

Within the serial link I/O controller there are three paritions of logic that operate on different frequency clocks. The processor bus interface logic, the transmit link logic and the receive link logic. The processor bus logic accepts commands from the processor for serial link operation. This logic must communicate these commands to the transmit link logic which initiates them.

A control state machine, which is located within the processor bus interface logic, changes state based on commands issued by the processor. A transmit state machine, located within the transmit link logic, changes state based on the control state machine 'states'. Fig. 1 shows the circuit that was designed to enable these two state machines to communicate.

The control 'states' first go through synchronizing latches that run on the tramsmit link frequency. There are two stages of latch so that any oscillation, due to metastability, of the first latch has settled by the time the second latch closes. The 'states' are then latched and a comparator is used to check that the new 'states' are valid for two cycles. This ensures that state transitions are not seen as ambiguous states. A holding latch i...