Browse Prior Art Database

Multi-Clocked Synching Data Buffer RAM

IP.com Disclosure Number: IPCOM000038046D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Peterson, MJ: AUTHOR [+4]

Abstract

Disclosed is a method of transferring electronic data across asynchronous logic boundaries through a RAM.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Multi-Clocked Synching Data Buffer RAM

Disclosed is a method of transferring electronic data across asynchronous logic boundaries through a RAM.

This transfer has a main chip controller to assign three asynchronous logic parititions to the RAM. This method provides asynchronous data transfer using the smallest amount of logic.

The data paths, address paths, and write clock are multiplexed to match whichever paritition has control at any given time. Actual switching is done by the main chip controller.

These are the key design issues:

- Each uniquely clocked control section must maintain its own address pointer. This pointer needs to be passed to other sections to indicate how much data is in the RAM. - The write clock switching must be designed with great care to prevent RAM timing problems due to skew/delay intro duced by the write clock multiplexer. - The buffer must be assigned to the main chip clock during LSSD and chip self-test. Thus, the other sections will lose some testability.

Disclosed anonymously.

1