Browse Prior Art Database

Multiply with Increment of the Multiplicand Operand

IP.com Disclosure Number: IPCOM000038047D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Cocanougher, D: AUTHOR [+2]

Abstract

Disclosed is a logical/physical implementation of the function (A operand) * (B operand + 0/1). The B operand may or may not be rounded by this invention.

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Multiply with Increment of the Multiplicand Operand

Disclosed is a logical/physical implementation of the function (A operand) * (B operand + 0/1). The B operand may or may not be rounded by this invention.

When the first instruction goes through the pipe, and a second instruction is waiting for its result, the second instruction does not want to wait until the first is completely finished with a Rounded IEEE Floating Point number.

Instruction #2 is waiting on the result of #1.

1. (Register 1) <-- (Register 5) + (Register 6)

2. (Register 2) <-- (Register 2) * (Register 7)

The last operation necessary for the mantissa of the first answer is the round. The sequence can be cut short if the operand is sent into the multiply of instruction #2 before any attempt to round is done. While the multiply is computing the result a late term can be added into the answer in the form of a multiplier operand. This accomplishes the increment.

Please refer to FIGURE #1.

The 1st instruction can lose absolutely no time to the rounding operation, and can circle the result into the mux after the normalization has completed. The Round operation sends a signal much later to the "AND GATE" which potentially gates another term late into the Multiply Array with no performance loss.

Disclosed anonymously.

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