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Offset Voltage Testing of Half-VDD Bit Lines

IP.com Disclosure Number: IPCOM000038052D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hurst, JA: AUTHOR

Abstract

Shorted bit lines of the half-VDD sensing design of dynamic random access memory prevents use of usual measurement of signal margin. By attaching transistors to data lines to apply an offset voltage pulse across the sense amplifier, signal margin can be measured accurately.

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Offset Voltage Testing of Half-VDD Bit Lines

Shorted bit lines of the half-VDD sensing design of dynamic random access memory prevents use of usual measurement of signal margin. By attaching transistors to data lines to apply an offset voltage pulse across the sense amplifier, signal margin can be measured accurately.

Referring to the figure, transistors T1 and T2 are turned on by offset pulse Vo to apply pulsed voltage V1 and V2 to data lines DLL and DLR. The remainder of the circuit is standard half-VDD design comprised of transistors T3 through T10 connected as shown to data lines DLL and DLR, bit lines BLL and BLR, and word lines WL1 and WL2. Transistors T8 and T9 are connected through node capacitors CN1 and CN2 to ground. Transistor T7 grounds transistors T5 and T6 during application of set pulse 2. Bit sense pulse 4 turns transistors T3 and T4 off during cycle start when set pulse 2 turns transistor T7 on and word lines receive pulse 6. Bit lines are shorted when pulse 8 is applied to the gate of transistor T10.

Signal margin is the difference voltage between V1 and V2 at which the sense amplifier cannot set correctly. By having devices T1 and T2 on the data lines instead of attaching separate devices on individual bit lines, space is saved and extra capacitive load on bit lines is avoided. By applying the offset voltage before wordlines are made active, cycle time is not extended; therefore, signal margin is measured in a real timing configuration. Note t...