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Technique for Reducing Personalized Array Soft Errors

IP.com Disclosure Number: IPCOM000038062D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

A soft error is a random, non-recurring error in a single bit of a memory array caused by alpha particles which create charges that act as leakage current in the memory cell. If the leakage current is high enough, the state of the memory cell is flipped, causing an error. "Qcrit" is defined as the amount of charge required to flip the state of a memory cell.

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Technique for Reducing Personalized Array Soft Errors

A soft error is a random, non-recurring error in a single bit of a memory array caused by alpha particles which create charges that act as leakage current in the memory cell. If the leakage current is high enough, the state of the memory cell is flipped, causing an error. "Qcrit" is defined as the amount of charge required to flip the state of a memory cell.

The present circuit (see figure) makes use of two transistors Tc and Td to increase the cell Qcrit to reach 180 to 200fc with only a slight increase in write path delay. The disclosed technique is DC testable.

Transistors Tc and Td function as diodes. In operation, diode Tc is reverse biased by connecting its anode (TP1) to a voltage that reverse biases the diode and gives the required capacitance relative to its cathode. Anode TP1 is connected to ground during operation for the application. The cathode of diode Tc is connected to output node Q1.

Diode Td is similarly connected to output node Q2 and TP2. Diodes Tc and Td increase the capacitance at output nodes Q1 and Q2. Respective nodes TP1 and TP2 from other cells in an array are dotted together and brought outside of the chip, so that they can be connected either to a test voltage during test mode or to ground during operation.

The procedure for testing the connections between transistors Tc and Td to the rest of the array cell is as follows.

For testing transistor Tc, perform the following steps:

a) W...