Browse Prior Art Database

Special Planar Manufacturing Tests in Ros

IP.com Disclosure Number: IPCOM000038160D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Denison, R: AUTHOR [+3]

Abstract

This disclosure describes that concept of eliminating the need for special test fixtures for new planar boards by using an improved Power On Self Test (POST) that logs the error codes, etc. in the nonvolatile storage provided by the Real Time Clock (RTC). When the planar is placed into the stress chamber, only power and memory need be connected to the the planar board. Once power is applied, POST clears the time in the RTC marking the beginning of the test. POST then begins looping on its self tests. When an error is encountered, POST logs the loop count and error code into the RTC.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 1

Special Planar Manufacturing Tests in Ros

This disclosure describes that concept of eliminating the need for special test fixtures for new planar boards by using an improved Power On Self Test (POST) that logs the error codes, etc. in the nonvolatile storage provided by the Real Time Clock (RTC). When the planar is placed into the stress chamber, only power and memory need be connected to the the planar board. Once power is applied, POST clears the time in the RTC marking the beginning of the test. POST then begins looping on its self tests. When an error is encountered, POST logs the loop count and error code into the RTC.

After the stress test is complete, the planar can be unplugged and moved to the Functional Verification Test station (FVT) where the test results are extracted from the RTC. The FVT test station can determine what errors occurred (if any), how often, and what time into the test the error occurred. The time of the error can be calculated by the loop count. Each loop of POST is 30 seconds in duration.

The POST code is modified to allow the power on self test code to maintain and log the following information into the RTC nonvolatile memory during manufacturing test. Part of the RTC memory locations can be used to log the test information because just the planar is being tested, not the complete system. The RTC memory map below describes the memory locations used and their function.

Location Function

0 - 5 Reset to 0 time at beginning of test

11-...