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Low Cost Silicon/Thin Film Wire Bonding Fanout Base

IP.com Disclosure Number: IPCOM000038187D
Original Publication Date: 1989-Dec-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Favata, AF: AUTHOR [+4]

Abstract

It is proposed to use Si wafers and thin film processes to make space transformers for low cost packaging of semiconductor devices. The method uses the wafers and processes instead of ceramic or decal type carriers with thin films.

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Low Cost Silicon/Thin Film Wire Bonding Fanout Base

It is proposed to use Si wafers and thin film processes to make space transformers for low cost packaging of semiconductor devices. The method uses the wafers and processes instead of ceramic or decal type carriers with thin films.

The structure is developed by laying down a thin layer of polyimide on top of an 82 or 125 mm Si wafer 1 - see Fig. 1. Wires in the mil range are deposited in a pattern which provides a connection between the chip's 2 C-4 pads 3 to pads arranged on the periphery of the Si base. The pads are arranged in an area matrix. The chips are mounted on the Si base and the chip and carrier inserted into a dual inline package DIP 4. Connections between the I/O's of the DIP and the peripheral arrangement of the pads on the carrier are effected by wire bonding 5.

The basic process revolves around a dielectric insulation applied to an Si substrate, thin film metallization to form the lines and pads, another layer of insulation, substrate ball- limiting-metallurgy (BLM), final passivation and via etch, dicing and C-4 joining. The final step is wire bonding to the next level of packaging.

The proposal: 1. provides a unified Si substrate chip/assembly with a matched thermal coefficient and low stress environment for the C-4 pads; 2. provides an inexpensive method for transferring array disposed C-4 pads to a peripheral arrangement; 3. provides a means to use a low-cost package; 4. does not require an i...