Browse Prior Art Database

High Drive Superslow Driver

IP.com Disclosure Number: IPCOM000038346D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+4]

Abstract

This article concerns the design of an inverting driver circuit having slow WV/Wt for the falling transition, during which any changes in the DC load current, e.g., for differing driver applications, may be accomodated without adverse effect on the transition. The designer is thus able to implement a slow WV/Wt circuit while having high DC drive. The drawing shows a high drive superslow driver circuit which allows any DC load current for slow WV/Wt. Key to its function is the operation of transistor T1 in saturation during the transition mode. When output A- falls to the zero level, T1 turns off automatically, turning off the transition control circuitry.

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High Drive Superslow Driver

This article concerns the design of an inverting driver circuit having slow WV/Wt for the falling transition, during which any changes in the DC load current, e.g., for differing driver applications, may be accomodated without adverse effect on the transition. The designer is thus able to implement a slow WV/Wt circuit while having high DC drive. The drawing shows a high drive superslow driver circuit which allows any DC load current for slow WV/Wt. Key to its function is the operation of transistor T1 in saturation during the transition mode. When output A- falls to the zero level, T1 turns off automatically, turning off the transition control circuitry. Design of the disclosed driver circuit rests on the simple differential current-switch receiver circuit composed of transistors TA, TB, TC and TD; transition control components D1, T1, T2 and D2, with resistors R2, R1 and R; and Darlington push-pull devices TX, TY and TZ. It should be noted that the transistor TCC and resistors RC1 and RC2 are employed as a DC clamp to prevent the output "1" level from going too high. This circuit operates as follows: Assume that input A is down such that receiver devices TA, TB and TC are off, causing TX and TY to conduct and establishing the logical "1" level at output - . Note here that transistor TD must conduct, keeping T2 and TZ off. When output - is at the logic "1" level, transistor T1 conducts and is operated in saturation due to the elimination of the SBD (Schottky Barrier Diode) from T1 and base drive is determined by resistors R, R1, and R2. As input A rises, transistors TA, TB and TC conduct, resulting in the turning off of Darlington's TX and TY and the transistor TD. Once TD turns off, its collector voltage begins to rise, establishing base current for transistor T2. Since T1 is in saturation, there are two...