Browse Prior Art Database

Image Processing Circuit

IP.com Disclosure Number: IPCOM000038354D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Asano, H: AUTHOR [+2]

Abstract

This article discloses an image processing circuit capable of fetching source data from a source memory area and writing the source data into a destination memory area on bit boundary basis with any angle. Fig. 1 shows source data fetched from the source memory area 1 shown in Fig. 2, destination data fetched from a destination memory area 2 into which the source data is written, and a mask pattern for controlling the write operation with an angle A. The source data could be fetched from the source memory area 1 on the bit boundary basis. The source data with any length could be fetched. The exemplary source data has one byte length and is called one-byte source data.

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Image Processing Circuit

This article discloses an image processing circuit capable of fetching source data from a source memory area and writing the source data into a destination memory area on bit boundary basis with any angle. Fig. 1 shows source data fetched from the source memory area 1 shown in Fig. 2, destination data fetched from a destination memory area 2 into which the source data is written, and a mask pattern for controlling the write operation with an angle A. The source data could be fetched from the source memory area 1 on the bit boundary basis. The source data with any length could be fetched. The exemplary source data has one byte length and is called one-byte source data. Address (Xs, Ys) of the one- byte source data, starting address (Xd, Yd) of the destination data, data representing height Hd, width Wd, distance D of the destination data and data representing the angle A are supplied to a control circuit 3 through address and data lines. The control circuit 3 responds to the data representing the angle A to assemble the mask pattern. The control circuit 3 fetches the one-byte source data from the source memory area 1 and stores it in a data shifter 4. The control circuit 3 fetches four bytes D1 through D4 from the destination memory area 2 and stores them in a data buffer 5. Next, the control circuit 3 supplies a control signal through a line 7 for transferring the first byte D1 from the data buffer 5 to a buffer 6. The control circuit 3 controls the shift operation of the data shifter 4 through a line 8 and specifies the bit position in the buffer 6 into which the...