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100% Available DRAM

IP.com Disclosure Number: IPCOM000038355D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Penoyer, RF: AUTHOR [+2]

Abstract

This article relates to memory applications where static random-access memory (SRAM) designs are chosen for their 100% availability (no need for refresh). Through the utilization of a unique dynamic random-access memory (DRAM) architecture, a lower cost solution is available. With DRAM cell densities at least 4X SRAM densities, a two-cell/ bit storage means, a small static buffer and some logic will result in a chip level cost and density advantage in favor of a 100% available DRAM architecture. The figure shows the 100% available DRAM architecture consisting of two independent memories A and B for storing two sets of identical data and a refresh cycle that alternates between the two memories.

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100% Available DRAM

This article relates to memory applications where static random-access memory (SRAM) designs are chosen for their 100% availability (no need for refresh). Through the utilization of a unique dynamic random-access memory (DRAM) architecture, a lower cost solution is available. With DRAM cell densities at least 4X SRAM densities, a two-cell/ bit storage means, a small static buffer and some logic will result in a chip level cost and density advantage in favor of a 100% available DRAM architecture. The figure shows the 100% available DRAM architecture consisting of two independent memories A and B for storing two sets of identical data and a refresh cycle that alternates between the two memories. In the event of a conflict between the need for a memory refresh cycle and the need for a memory read access, the system will logically steer the data set address to the memory bank not in a refresh mode. When a write memory conflicts with a memory refresh cycle, the write address and data are stored in a buffer register as well as being written in the DRAM which is not in a refresh mode. The buffer register contents are subsequently written into the alternate memory bank immediately following the completion of its refresh cycle. The buffer register to DRAM data transfer time is designed so that the write period is slightly faster than the time required for a direct write to a DRAM. Within a refresh period, a continuous system write operation will "catch...