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Parity Generator Integrated With Latches

IP.com Disclosure Number: IPCOM000038357D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Moser, JJ: AUTHOR

Abstract

A method is described for implementing a parity function in conventional level sensitive scan design (LSSD) shift register latch (SRL) strings allowing simple diagnosis of single-bit faults. The method consists of adding an exclusive OR (XOR) gate to an LSSD SRL and of a technique of interconnecting the added XOR gates to comprise a parity generator for all latches on a chip. An LSSD SRL is a master-slave latch which is synchronized with two phase clocks, hereinafter referred to as clocks C and B, plus an auxiliary port provided to a master latch which is synchronized with a third clock, referred to as the A clock. The clocks are omitted from the figures. The data into the auxiliary port is either connected to a primary input or else the output of another slave latch.

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Parity Generator Integrated With Latches

A method is described for implementing a parity function in conventional level sensitive scan design (LSSD) shift register latch (SRL) strings allowing simple diagnosis of single-bit faults. The method consists of adding an exclusive OR (XOR) gate to an LSSD SRL and of a technique of interconnecting the added XOR gates to comprise a parity generator for all latches on a chip. An LSSD SRL is a master-slave latch which is synchronized with two phase clocks, hereinafter referred to as clocks C and B, plus an auxiliary port provided to a master latch which is synchronized with a third clock, referred to as the A clock. The clocks are omitted from the figures.

The data into the auxiliary port is either connected to a primary input or else the output of another slave latch. The output of the last slave latch is brought to a primary output pin. Thus connected, the LSSD SRL comprises one or more shift registers on the chip such that data can be loaded into or out of the LSSD SRL by alternately clocking A and B and by controlling the value on scan in and observing the value on scan out. The resultant "scan" feature of LSSD is used primarily to improve testing by providing a simple means for initializing latches to desired values and also for determining the values in the latches. Testing chips with LSSD relies heavily on scanning into and out of the latches. If a chip is defective such that data can not be scanned through the latches, testing can not be completed and diagnosis of the defect is extremely difficult. The initial benefit of adding a parity generator is to improve diagnosis in this situation. An XOR gate is included with every LSSD SRL as shown in Fig.1. At the chip level, PARIN(n) is connected to PAROUT(n-1), etc. The first latch PARIN(1) is connected to signals such as scan in, a primary input, or simply to a fixed voltage. The last latch PAROUT(m) is brought off the chip as an output to be observed during test. The added XOR circuits thus interconnected at the chip level comprise a parity generator for all latches on the chip. That is, the output PAROUT(m) from the last latch represents the parity bit of all bits stored in all m latches on the chip. As data is scanned into the latches on the chip, the PAROUT(m) is observed to change continuously until a bad bit is encountered, at which point PAROUT(m) stops changing. The point at which PAROUT(m) stops changing is used to identify a bad bit on a defective chip.

Extended use of this method at a higher packaging level is accomplished by connecting the PAROUT(m) output of one chip to the PARIN(1) input of the next chip until all chips are interconn...