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Decoded Bitline Structures for High Performance Sensing in Semicon-Ductor Dynamic Memory

IP.com Disclosure Number: IPCOM000038370D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR

Abstract

A decoded bitline structure is described which gives smaller bitline capacitance before sensing, faster signal transfer from bitlines to I/O bus, and does not need extra depletion devices and extra PMOS cross- coupled latches. As the density of DRAM (dynamic random-access memory) chips increases, the number of memory cells (bits) associated with the first- stage sense amplifier also has increased. The reason for this increase is that as the memory cell size becomes smaller, the peripheral-circuit overhead should be reduced by decreasing the number of sense amplifiers and column decoders. However, as the number of bits per bitline increases, either the differential signal for sensing becomes smaller or the cell capacitance has to be increased.

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Decoded Bitline Structures for High Performance Sensing in Semicon- Ductor Dynamic Memory

A decoded bitline structure is described which gives smaller bitline capacitance before sensing, faster signal transfer from bitlines to I/O bus, and does not need extra depletion devices and extra PMOS cross- coupled latches. As the density of DRAM (dynamic random-access memory) chips increases, the number of memory cells (bits) associated with the first- stage sense amplifier also has increased. The reason for this increase is that as the memory cell size becomes smaller, the peripheral-circuit overhead should be reduced by decreasing the number of sense amplifiers and column decoders. However, as the number of bits per bitline increases, either the differential signal for sensing becomes smaller or the cell capacitance has to be increased. One solution widely used now is to multiplex two bitlines on two sides of the sense amplifier through decoupling devices, for example, depletion devices Q3, Q4, Q5 and Q6 in Fig. 1. Before the sensing starts, one bitline is decoupled from the sense amplifier by turning off the decoupling devices (for example, Q3 and Q4) so that the bitline capacitance for the charge transfer ratio can be smaller to give large sensing signal. After the differential signal has been amplified, the latching clock must trigger the dMLR clock to turn on Q3 and Q4 such that the signal can propagate to the I/O bus when the selected column switch is turned on. As the number of bits increases, the above bit-line structure has two inadequacies for high performance sensing:
(1) The differential-signal

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transfer from bit-line to the I/O bus is not fast. First, if the signal builds up on the bitline which is on the side of the sense amplifier not connected to the column switch, it can propagate to the column switch only after Q3 and Q4 are turned on, which involves clocking delays. Second, the signal build-up on the I/O bus before I/O sensing depends on the swing of the entire bitline capacitance.
(2) Even if the bitline has been multiplexed, its capacitance still can be large for high density memory. This article describes a new decoded bitline structure which can solve the above problems. This new decoded bitline structure is shown in Fig. 2. The bitline is divided into multiple sections (four are shown) which are located on one side of the sense amplifier. The first section (1BL and 1BLN) closest to the sense amplifier, is connected to the sense amplifier by the interconnection level #1 (which can be polycide, aluminum or tungsten, or diffusion) through decoupling devices Q1 and Q2 (depletion NMOS devices are used here but other suitable devices may be used as described later). The second, third, and fourth sections are connected by interconnect level #1, the decoupling devices, and interconnection level #2 (which can be aluminum, tungsten or polycide) to the sense amplifier. The decoupling devices are controlled by...