Browse Prior Art Database

Masterslice Concept for VLSI Chips

IP.com Disclosure Number: IPCOM000038372D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Pollmann, K: AUTHOR [+4]

Abstract

Masterslices or gate arrays comprise a matrix of similar components. Personalized functions are obtained by customer-specific wiring, using metallization masks. The masterslice layers are manufactured in large series. The wafers are put on stock in semimanufactured form. Wiring is effected in small series. VLSI chips require at least two wiring layers. In most cases, personalization is carried out as follows: 1) First metallization - via - second metallization. 2) Contacts - first metallization - via - second metallization. The higher the degree of personalization, the smaller the chip size may be. Particularly for changes made for eliminating design errors, the time at which the changed chip is reavailable is essential.

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Masterslice Concept for VLSI Chips

Masterslices or gate arrays comprise a matrix of similar components. Personalized functions are obtained by customer-specific wiring, using metallization masks. The masterslice layers are manufactured in large series. The wafers are put on stock in semimanufactured form. Wiring is effected in small series. VLSI chips require at least two wiring layers. In most cases, personalization is carried out as follows: 1) First metallization - via - second metallization.

2) Contacts - first metallization - via - second

metallization. The higher the degree of personalization, the smaller the chip size may be. Particularly for changes made for eliminating design errors, the time at which the changed chip is reavailable is essential. If a circuit is manufactured in small numbers, the cost of the personalized masks becomes excessive. In VLSI masterslice chips not all semimanufactured gates can be wired. If such chips are personalized at low density, the wiring data can be automatically generated at high speed. At high chip densities, however, time is consumed by placing and manually completing non-wired networks as well as by subsequent changes, if any. A diagram of a masterslice concept with a first metallization is shown in Fig. 1 and with a second metallization and vias to the first metallization in Fig. 2. The first metallization mask for the first metallization to be applied to wafer 1, comprising transistor structures 2, is manufactured...