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Simplified Static Column Decoder for CMOS Memory Bit Switches

IP.com Disclosure Number: IPCOM000038385D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Redman, TM: AUTHOR [+2]

Abstract

This article relates to a simplified column decoder used to control bit switches in complementary metal-oxide-semiconductor (CMOS) memories by reducing circuit count, area and predecoder loading. A higher density memory is possible by reducing device counts, resulting in less chip area and power required for bit switch decoding. This is done by modifying the CMOS NAND static column decoder circuit. Shown in Fig. 1 is a basic CMOS NAND column decoder circuit design used in many current memory designs. Predecoder lines (Zx) and line A8C and A8C not drive decoder transistors 0-4 and 0'-4'. P type pull-up transistors (0'-4') are used to minimize active CMOS NAND power requirements, but increase the number of decoder devices and double the load on predecoder drive circuits.

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Simplified Static Column Decoder for CMOS Memory Bit Switches

This article relates to a simplified column decoder used to control bit switches in complementary metal-oxide-semiconductor (CMOS) memories by reducing circuit count, area and predecoder loading. A higher density memory is possible by reducing device counts, resulting in less chip area and power required for bit switch decoding. This is done by modifying the CMOS NAND static column decoder circuit. Shown in Fig. 1 is a basic CMOS NAND column decoder circuit design used in many current memory designs. Predecoder lines (Zx) and line A8C and A8C not drive decoder transistors 0-4 and 0'-4'. P type pull-up transistors (0'-4') are used to minimize active CMOS NAND power requirements, but increase the number of decoder devices and double the load on predecoder drive circuits. The increased load on node N4, by using pull-up devices, slows down the performance of a static column decoder. Transistor 5 is a leakage path to ground which prevents node N4 from floating and transistors 6 and 7 invert the circuit output. This CMOS NAND decoder circuit design is repeated for each column decoder needed in a memory array design. Fig. 2 is a modification of the column decoder shown in Fig. 1. The new modified CMOS NAND decoder has one of the address decode transistors (1), shown in Fig. 1, removed. The predecoded input line (Z12) that used to drive transistor 1 is inverted and connected to what would normally be Vss (Fig....