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Split Emitter MTS Memory Cell

IP.com Disclosure Number: IPCOM000038389D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

An array cell has been developed for semiconductor devices which is smaller and faster than conventional cells. It is a merged transistor switch (MTS) cell with cross-coupled PNP's, split PNP emitters, and NPN loads. In conventional MTL cells a discharge process is required for access [*]. This leads to delays and circuit complexities. The complementary transistor switch (CTS) cell is fast in read, but the cell size is relatively large. The write, meanwhile, is slow unless the NPN Tx b is artificially degraded. The proposed MTS cell is free from the foregoing problems, having combined features of the MTL and CTS cells. As compared to conventional CTS cells, no separate I/O devices are required in the configuration (Fig. 1).

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Split Emitter MTS Memory Cell

An array cell has been developed for semiconductor devices which is smaller and faster than conventional cells. It is a merged transistor switch (MTS) cell with cross-coupled PNP's, split PNP emitters, and NPN loads. In conventional MTL cells a discharge process is required for access [*]. This leads to delays and circuit complexities. The complementary transistor switch (CTS) cell is fast in read, but the cell size is relatively large. The write, meanwhile, is slow unless the NPN Tx b is artificially degraded. The proposed MTS cell is free from the foregoing problems, having combined features of the MTL and CTS cells. As compared to conventional CTS cells, no separate I/O devices are required in the configuration (Fig. 1). The injectors to the flip-flop are used as read/write devices during access, with the general operation being similar to the split emitter MTL cells. In standby operation, the bit rails are maintained at a fixed voltage level about one VBE above the word line (Fig. 1). The cell amounts to two PNP inverters feeding each other with current drains provided by transistors 3 and 4. The stability requirement is bPNP >1. In access, the selected word line is pulled down. If it is assumed that transistor 1 is on, transistor 3 is saturated, then transistor 2 is off and transistor 4 is the linear current sink. For READ, both bit rails are pulled downward, with one side pulled down further. The bit rail voltage difference is...