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Browse Prior Art Database

Self-Aligned, Shallow Junction Bipolar Structure

IP.com Disclosure Number: IPCOM000038392D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Lechaton, J: AUTHOR [+3]

Abstract

The self-aligning base etching scheme described in this article permits the fabrication of very thin base-width bipolar devices, providing both a low extrinsic base resistance and self-alignment of the contact metallurgy to the device contacts. In addition to a narrow intrinsic base, the disclosed device structure also offers improved device performance and density and a planar structure over the device area after metallization. The procedure disclosed consists essentially of diffusing a base in and subsequently removing a portion of it by controlled etch. This involves the addition of a relatively few process steps to the current technology for its implementation, available techniques being employed to form the base and emitter. In reference to Fig.

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Self-Aligned, Shallow Junction Bipolar Structure

The self-aligning base etching scheme described in this article permits the fabrication of very thin base-width bipolar devices, providing both a low extrinsic base resistance and self-alignment of the contact metallurgy to the device contacts. In addition to a narrow intrinsic base, the disclosed device structure also offers improved device performance and density and a planar structure over the device area after metallization. The procedure disclosed consists essentially of diffusing a base in and subsequently removing a portion of it by controlled etch. This involves the addition of a relatively few process steps to the current technology for its implementation, available techniques being employed to form the base and emitter. In reference to Fig. 1, a thin CVD (chemical vapor deposited) nitride (N1000 ~ or less) is applied to the structure, followed by a 1.2- micron thick layer of CVD polysilicon, which is, in turn, covered by 2500 ~ of CVD Si3N4, or more (to ensure that it sufficiently withstands the subsequent nitride RIE steps to be used). A photoresist mask N 1-micron thick or more is thereafter employed to RIE the nitride and polysilicon, with endpoint detection on the nitride layer under the polysilicon. Sidewall oxide studs are then formed in the polysilicon, preferably using high pressure oxidation. The emitter and collector areas are then RIE/dip etched. The RIE of silicon is continued to a depth of 80...