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Stacked Technology for Random-Access Memory Construction

IP.com Disclosure Number: IPCOM000038394D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Koburger, C: AUTHOR [+3]

Abstract

By using a method described in "Silicon-on-insulator (SOI) by Bonding and Etch-back" by J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathy, pp. 684-687, International Electron Devices Meeting of IEEE, Washington, D.C., December 1-4, 1985, a high quality single crystal silicon layer is bonded to planarized oxide (glass) over a first level of integrated circuitry. By then creating devices and circuits in and on the bonded silicon layer, e.g., complementary metal-oxide-semiconductor (CMOS) support circuitry for a first level of n-type metal- oxide-semiconductor (NMOS) random-access memory (RAM) and connecting the two levels of circuitry through via holes in the bonding oxides, a very high density memory array is achieved. As is shown in the figure, a circuit structure is created on a first silicon substrate 2.

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Stacked Technology for Random-Access Memory Construction

By using a method described in "Silicon-on-insulator (SOI) by Bonding and Etch-back" by J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathy, pp. 684-687, International Electron Devices Meeting of IEEE, Washington, D.C., December 1-4, 1985, a high quality single crystal silicon layer is bonded to planarized oxide (glass) over a first level of integrated circuitry. By then creating devices and circuits in and on the bonded silicon layer, e.g., complementary metal-oxide-semiconductor (CMOS) support circuitry for a first level of n-type metal- oxide-semiconductor (NMOS) random-access memory (RAM) and connecting the two levels of circuitry through via holes in the bonding oxides, a very high density memory array is achieved. As is shown in the figure, a circuit structure is created on a first silicon substrate 2. The portion of the circuitry shown contains a recessed oxide region 4 with a conductive line 6 disposed above it. Another conductive line 8 is insulated from an overlapping conductive layer 10, the substrate 2 and a nearby diffusion 12. The conductive materials are refractories, e.g., polysilicon, silicides, or refractory metals. A layer of glass 14 is applied and planarized. As is described in the reference, a lightly doped epitaxial layer of silicon (epi) is formed on a highly doped silicon wafer. The epi is oxidized and bonded to the planarized glass 14 by heat treatment in the 700- to 1000...