Browse Prior Art Database

Reduce Jitter in Ros-Synthesized Clocks by Using Delay Lines

IP.com Disclosure Number: IPCOM000038397D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Anderson, RB: AUTHOR

Abstract

In a hardware system where the main oscillator is of one fixed frequency and other clocks are required that are not simple sub-frequencies, a read-only storage module can be used to generate these clocks. However, an amount of clock jitter, which may be unacceptable, is introduced when this method is used. This disclosure presents a technique to reduce this jitter. (Image Omitted) As shown in Fig. 1, different frequency clocks can be generated by using a read-only storage (ROS) module and the bits in the different address locations coded to generate the desired frequencies. When the desired frequencies are sub-multiples of the system clock, there is no jitter associated with the generated clocks, but some of the clocks could be asymmetrical. In Fig. 1, clocks B and D are asymmetrical.

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Reduce Jitter in Ros-Synthesized Clocks by Using Delay Lines

In a hardware system where the main oscillator is of one fixed frequency and other clocks are required that are not simple sub-frequencies, a read-only storage module can be used to generate these clocks. However, an amount of clock jitter, which may be unacceptable, is introduced when this method is used. This disclosure presents a technique to reduce this jitter.

(Image Omitted)

As shown in Fig. 1, different frequency clocks can be generated by using a read-only storage (ROS) module and the bits in the different address locations coded to generate the desired frequencies. When the desired frequencies are sub-multiples of the system clock, there is no jitter associated with the generated clocks, but some of the clocks could be asymmetrical. In Fig. 1, clocks B and D are asymmetrical.

(Image Omitted)

When one needs to generate a clock that is not a true sub-multiple of the system clock, an undesirable amount of jitter can be generated. Consider having a system clock of 12.352 MHz and wanting to generate a clock with a frequency of 3.6864 MHz. The procedure for generating the ROS bit pattern is shown in Figs. 2 and 3. Synthesized clock = 3.6864 MHz = 288 :Lowest Common (1)

System clock 12.352 MHz 965 Denominators Thus, the ROS should have 965 addresses. The minimum number of system clock periods to generate one synthesized clock period: Period = 965 : 288 = 3.350... = 3 (2) The number of system clock pulses that have to be "slipped" or "skipped": Skipped pulses = 965 - (3x288) = 101 (3) Each synthesized clock period will be at least three system clock periods and 101 of them will be four system clock periods in duration. Note that: (101x4)+(187x3)=965 (4) 101+187 =288 (5) To obtain the desired result, disperse the 101 4-wide periods evenly among the 187 3-wide periods, so that: 288 : 3 = 96 (6) If one makes every third synthesized clock period four system periods wide it will take (96x4)+(192x3)=960 system periods.
(7) This leaves five system periods yet to be "slipped" or: 965 = 193
(8)

5 Thus, one should slip one system clock every N 193 periods or slip...