Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

New Wiring Scheme for a Submicron FET Masterslice

IP.com Disclosure Number: IPCOM000038417D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+2]

Abstract

This article describes a technique to improve wiring and circuit density in a masterslice design to the level of a masterimage design. Use of a masterslice (also called gate array) for logic implementation can achieve fast turn-around-time both on circuit design and chip fabrication as compared to a semi-custom masterimage design or a (Image Omitted) handhorn custom design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

New Wiring Scheme for a Submicron FET Masterslice

This article describes a technique to improve wiring and circuit density in a masterslice design to the level of a masterimage design. Use of a masterslice (also called gate array) for logic implementation can achieve fast turn-around- time both on circuit design and chip fabrication as compared to a semi-custom masterimage design or a

(Image Omitted)

handhorn custom design.

However, the trade-off of using a masterslice design is its poor circuit density relative to the others. In this article we will describe a wiring technique to improve circuit density in a masterslice design. As circuit integration continues to increase in a VLSI chip, it seems that a masterslice design would diminish its role in logic applications. However, on the contrary, it gradually becomes clear that a masterslice design is essential to the development of a VLSI system. A VLSI system typically consists of few common VLSI chips, such as CPU, MMU (Memory Management Unit) chips, and some specific interface LSI chips depending on a system configuration. For example, the interface chips can be as simple as a printer controller or as complex as a multi-processor bus controller.

Consequently, from a system development viewpoint, it would be more economical to use a masterslice design to implement its specific interface chips during system development and evaluation. Integrating all the interface chips with CPU and MMU to achieve a system-level integration would not come until a system is well-developed on its board-level using masterslice chips. Most likely, final system cost as well as product volume will determine whether or not to pursue system-level of integration, rather than other technical reasons. Also, as FET technology continues to migrate into submicron domain, E-beam tool becomes one of the essential elements to achieve submicron pattern definition. The long turn-around-time of using E- beam tools for chip fabrication is expected to become a significant trade-off of using submicron high-speed logic circuits. A masterslice design approach will significantly increase hardware availability. Furthermore, a masterslice design is less sensitive to process defects because bad transistors can be easily excluded during circuit wiring. The following illustrates a way of achieving a masterimage-like wiring density in a masterslice design. A masterslice typically consists of rows of transistor arrays and wiring channels. The arrangement of transistors in a transistor array (or an array cell) can vary from just a few transistors to a continuous transistor array across a whole chip. However, in spite of the freedom of pre-arranging transistors, the locations for accessing...