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Producing Glitchless Output From a Data Multiplexer in the Generation of Computer Memory Addresses

IP.com Disclosure Number: IPCOM000038419D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Sotolongo, H: AUTHOR

Abstract

A technique is described whereby glitches are eliminated from data multiplexer (MUX) outputs as the control of the MUX switches to select another data input or when the control function itself is not glitch- free. Some control data lines in a computer storage unit must be stable for relatively long time windows as the memory chips are being accessed. The concept described herein eliminates periods of instability or glitches from one such set of lines while satisfying the speed constraints typically associated with those signals. One way of providing a glitch-free control and address function would be to add a latch circuit to the timing path to provide stability to the address lines. However, this approach would conflict with the speed requirement.

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Producing Glitchless Output From a Data Multiplexer in the Generation of Computer Memory Addresses

A technique is described whereby glitches are eliminated from data multiplexer (MUX) outputs as the control of the MUX switches to select another data input or when the control function itself is not glitch- free. Some control data lines in a computer storage unit must be stable for relatively long time windows as the memory chips are being accessed. The concept described herein eliminates periods of instability or glitches from one such set of lines while satisfying the speed constraints typically associated with those signals. One way of providing a glitch-free control and address function would be to add a latch circuit to the timing path to provide stability to the address lines. However, this approach would conflict with the speed requirement. Therefore, the latch circuit approach was not chosen in favor of the technique described herein.

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In one case, the cause of the glitch is the discontinuity in the MUX control as one control disappears before the other MUX control takes over. In another case, discontinuities occur in one of the control lines as the system increments past the different states of an operation. To eliminate glitches in both cases, the logic diagram shown in Fig. 1 illustrates the use of a signal to bridge the discontinuity. Timing diagrams, as shown in Fig. 2, illustrate how in both cases the use of the bridge signal eliminates...