Browse Prior Art Database

Low Barrier Schottky Clamped Complementary DTL Circuit

IP.com Disclosure Number: IPCOM000038433D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Balyoz, J: AUTHOR [+2]

Abstract

The LCDTL (low barrier Schottky clamped complementary diode-transistor logic) circuit shown in the drawing features a 60% improvement in delay (at 100-mwatt power level) and a 70% improvement in power (at 1-nsec delay level) over DTL circuits. Its operation is basically similar to that of DTL, except for the addition of a PNP transistor, T1, at the output stage to obtain complementary drive. T1 can be integrated with NPN output transistor T2 . As shown, it is clamped out of saturation with DL2, an LSBD (low barrier Schottky diode), thereby lowering the up level at the output of the circuit, and as noted previously, considerably improving the power delay product of LCDTL over that of DTL.

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Low Barrier Schottky Clamped Complementary DTL Circuit

The LCDTL (low barrier Schottky clamped complementary diode-transistor logic) circuit shown in the drawing features a 60% improvement in delay (at 100- mwatt power level) and a 70% improvement in power (at 1-nsec delay level) over DTL circuits. Its operation is basically similar to that of DTL, except for the addition of a PNP transistor, T1, at the output stage to obtain complementary drive. T1 can be integrated with NPN output transistor T2 . As shown, it is clamped out of saturation with DL2, an LSBD (low barrier Schottky diode), thereby lowering the up level at the output of the circuit, and as noted previously, considerably improving the power delay product of LCDTL over that of DTL.

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