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Accurate Measurement of the Effective Inductance of a Power Pad at the Chip Level

IP.com Disclosure Number: IPCOM000038443D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+4]

Abstract

A technique has been developed to obtain more accurate impedance characterization of electrical packages of semiconductor devices. Since package inductances are typically very low, e.g., in the range of a few nanohenries only, very high frequency signals are needed to develop sufficient voltages across them for accurate measurements. However, effects of parasitic reactances and probe impedance makes direct measurement of such high frequency voltages prone to errors. The technique outlined below overcomes above limitations and permits more accurate measurement of such small inductances. Referring to the block schematic shown in Fig. 1, two power supply pins coated at the bottom surface of a package (module) are represented by the lines labeled 'VCC supply' and 'VR supply'.

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Accurate Measurement of the Effective Inductance of a Power Pad at the Chip Level

A technique has been developed to obtain more accurate impedance characterization of electrical packages of semiconductor devices. Since package inductances are typically very low, e.g., in the range of a few nanohenries only, very high frequency signals are needed to develop sufficient voltages across them for accurate measurements. However, effects of parasitic reactances and probe impedance makes direct measurement of such high frequency voltages prone to errors. The technique outlined below overcomes above limitations and permits more accurate measurement of such small inductances. Referring to the block schematic shown in Fig. 1, two power supply pins coated at the bottom surface of a package (module) are represented by the lines labeled 'VCC supply' and 'VR supply'. Inductances of the associated power distribution networks buried inside the module are represented by lumped inductances labeled L1 through L4. Care is taken during design of the module to minimize (preferably eliminate altogether) mutual couplings between L1/L2 and L3/L4; the grounded shields shown next to L1 and L3 represent no mutual couplings. During test, a high frequency signal S1 of frequency F1, typically in the several-hundred- megahertz range, is fed to the chip via an external signal generator (SIG GEN).

It is amplified in (AMP) amplifier 4 and fed to the top surface of the module's power distribution system, i.e., to the other ends of L2 and L3, via a small resistor R (typically less than 10 ohms) as shown, so that the high frequency current flows through L2 and R in series. Voltage developed across L2 is fed to input ...