Browse Prior Art Database

Use of a Tri-State Bit Decoder to Improve Bit-Address Read Access Time

IP.com Disclosure Number: IPCOM000038458D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Eardley, DB: AUTHOR [+2]

Abstract

A method is described to reduce the bit-line discharging time without substantially increasing the DC power of random-access memory (RAM) devices. In large high speed bipolar static RAM devices a significant portion of the bit-address read access time (Tacc') may be consumed at the bit line decoding stage. This is because the selected bit lines have to be discharged. The circuitry shown in the figure uses a tri- state bit decoder to reduce the discharging time. Used in conjunction with an address clock, the tri-state bit decoder functions in the same way as a conventional bit decoder. When the address clock is active during a read/write cycle, the decoder provides two logic states: high for deselection and low for selection. When the address clock is non-active, the decoder outputs an intermediate logic level.

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Use of a Tri-State Bit Decoder to Improve Bit-Address Read Access Time

A method is described to reduce the bit-line discharging time without substantially increasing the DC power of random-access memory (RAM) devices. In large high speed bipolar static RAM devices a significant portion of the bit- address read access time (Tacc') may be consumed at the bit line decoding stage. This is because the selected bit lines have to be discharged. The circuitry shown in the figure uses a tri- state bit decoder to reduce the discharging time. Used in conjunction with an address clock, the tri-state bit decoder functions in the same way as a conventional bit decoder. When the address clock is active during a read/write cycle, the decoder provides two logic states: high for deselection and low for selection. When the address clock is non-active, the decoder outputs an intermediate logic level. In this way all the bit lines are preset to a level between the selected and deselected levels prior to an active cycle. When the active cycle arrives, the deselected bit lines are pulled up to the deselected level while the selected bit lines are discharged down to the selected level. The discharge time has been substantially shortened since the bit lines were preset at a lower level relative to the unselected level. In experimental work, an array cross-section of 128 bits/bit line was used with Tacc' simulated for a 16 Kb bipolar static RAM design using the Harper cell. Under identica...