Browse Prior Art Database

Clustering Drain Line for Harper Array

IP.com Disclosure Number: IPCOM000038460D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Eardley, DB: AUTHOR [+2]

Abstract

A layout and electrical circuit design technique have been developed for minimizing the variation of differential voltages across the cell between the word line and drain line in semiconductor devices. This makes it possible to eliminate the emitter resistor (RE), thereby saving space on the chip. Because of the word line and drain line resistance the voltage across an array of cells will not be equal. This causes the cell currents to vary from one cell to the other, which may affect the stability of the cell. In the design of the Harper cell an RE is usually used to avoid this current hogging. While the RE is effective, it has the disadvantage of occupying space on the chip which may be better utilized.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 80% of the total text.

Page 1 of 2

Clustering Drain Line for Harper Array

A layout and electrical circuit design technique have been developed for minimizing the variation of differential voltages across the cell between the word line and drain line in semiconductor devices. This makes it possible to eliminate the emitter resistor (RE), thereby saving space on the chip. Because of the word line and drain line resistance the voltage across an array of cells will not be equal. This causes the cell currents to vary from one cell to the other, which may affect the stability of the cell. In the design of the Harper cell an RE is usually used to avoid this current hogging. While the RE is effective, it has the disadvantage of occupying space on the chip which may be better utilized. In the development the approach taken to eliminate the RE is to segment the drain line and utilize several current sources for each segment. The reduced resistance as well as the reduced total current through each segment significantly reduces the voltage variation across the cell. In the prior arrangement, a row of 72 cells 1 (Fig. 1A) is connected to a word line 2. The current source 4 is connected to the other end of the drain line 3. The maximum voltage variation (dV) across the cells is where: In the development the drain line may be divided into 9 segments 7 (Fig. 1B) with each connected to 8 cells 8. The number of segments as well as the number of cells per segment is dependent on the array design and the layout. The...