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Frame Switching Node Matrix Mechanism

IP.com Disclosure Number: IPCOM000038475D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Blanc, A: AUTHOR [+2]

Abstract

This mechanism is used in a high performance network composed of traditionnal network access nodes connected through one or several frame switching nodes (FSN) which realize the network transit function. The main characteristics of the FSN are: Multiplexing of HDLC frames of variable length. . Routing of the incoming HDLC (high level data link control) frame to the selected output line according to the routing tag information included in the transmission header of each frame. . No error recovery. Frame drop in case of overflow. This matrix mechanism is designated to interconnect in the FSN all input line adapters to all output line adapters, without contention. Once the frame routing tag is analyzed, the destination register (DEST.REG.

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Frame Switching Node Matrix Mechanism

This mechanism is used in a high performance network composed of traditionnal network access nodes connected through one or several frame switching nodes (FSN) which realize the network transit function. The main characteristics of the FSN are: Multiplexing of HDLC frames of variable length. . Routing of the incoming HDLC (high level data link control) frame to the selected output line

according to the routing tag information included

in the transmission header of each frame. . No error recovery. Frame drop in case of overflow. This matrix mechanism is designated to interconnect in the FSN all input line adapters to all output line adapters, without contention. Once the frame routing tag is analyzed, the destination register (DEST.REG.)is loaded with the physical address of the destination output provided by the routing tag analysis. The decoder (DECODE) selects the transfer path of the current frame. After start order, the frame is transferred from the input line adapter to the output line adapter under the flag detection control. The path is reset at the detection of the closing flag. The transfer is started when the output is not busy, and only one frame is transferred to one output at a time. Several frames may be transferred simultaneously through the matrix if the output destination is different. This mechanism may be improved by using a modular approach whereby a number of Frame Switching Node Matrices are in turn them...