Browse Prior Art Database

Frame Switching Node Architecture

IP.com Disclosure Number: IPCOM000038481D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Blanc, A: AUTHOR [+2]

Abstract

This architecture is used in a high performance network composed of traditionnal network access nodes connected through one or several frame switching nodes (FSNs) which realize the network transit function. The main characteristics of the FSN are: . Multiplexing of HDLC (high level data link control) frames of variable length. . Routing of the incoming HDLC frame to the selected output line according to the routing tag information included in the transmission header of each frame. No error recovery. Frame drop in case of overflow. The main characteristics of this architecture are described hereunder. Frames are memorized and transferred including opening flag, closing flag and inserted zeros. Internal dataflow is controlled by flag detection.

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Frame Switching Node Architecture

This architecture is used in a high performance network composed of traditionnal network access nodes connected through one or several frame switching nodes (FSNs) which realize the network transit function. The main characteristics of the FSN are: . Multiplexing of HDLC (high level data link control) frames of variable length. . Routing of the incoming HDLC frame to the selected output line according to the routing tag

information included in the transmission header of

each frame. No error recovery. Frame drop in case of overflow. The main characteristics of this architecture are described hereunder. Frames are memorized and transferred including opening flag, closing flag and inserted zeros. Internal dataflow is controlled by flag detection. Internal data path is determined by routing tag analysis. The principle of operation is to establish dynamically a virtual shift register, from input to output, for one frame transfer time. Incoming frames are sequentially loaded in an input queue with only one opening flag and one closing flag. When one frame is completed in input queue, it is transferred to the frame analysis buffer. Routing tag analysis is performed at this level.

After analysis of the routing tag, the path is marked through the logical switching matrix, and the frame is transferred from the frame analysis buffer to the output queue. For each couple of data terminals, the path through the matrix is unique. When ready, th...