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Elimination of Disturbances in Charge-Buffered Logic

IP.com Disclosure Number: IPCOM000038483D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Wendel, DF: AUTHOR [+2]

Abstract

This article relates generally to integrated bipolar logic circuits and, more particularly, to reducing the susceptibility of such circuits to transient noise signals. Bipolar complementary transistor logic circuits with low power dissipation, also known as charge buffered logic circuits, are made less sensitive to slight variations in output impedance by providing a charge storage device to supply additional current to the output stage necessary to maintain a steady voltage level. A bipolar NAND circuit is shown in Fig. 1 having input charge storage diodes D1, D2 and decoupling charge storage diode D3, each having a time constant TS1. Diode D3 is connected to the bases of NPN transistor T1 and PNP transistor T2 that are arranged as an output push-pull inverter.

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Elimination of Disturbances in Charge-Buffered Logic

This article relates generally to integrated bipolar logic circuits and, more particularly, to reducing the susceptibility of such circuits to transient noise signals. Bipolar complementary transistor logic circuits with low power dissipation, also known as charge buffered logic circuits, are made less sensitive to slight variations in output impedance by providing a charge storage device to supply additional current to the output stage necessary to maintain a steady voltage level. A bipolar NAND circuit is shown in Fig. 1 having input charge storage diodes D1, D2 and decoupling charge storage diode D3, each having a time constant TS1. Diode D3 is connected to the bases of NPN transistor T1 and PNP transistor T2 that are arranged as an output push-pull inverter. Assuming that both inputs D1 and D2 are at their up levels, T1 is on, being fed by small base current I1-I2. If the output voltage Vout should rise slightly due to noise or switching in a subsequent connected circuit, there is insufficient steady-state base current available at T1 to hold the output voltage constant. A solution, however, is to provide charge storage diode D4 having a time constant TS2 approximately one tenth that of diode D1, D2 or D3. Diode D4 can supply an additional dynamic base current to steady-state base current I1-I2 that is proportional to its time constant TS2. With this addition, the turn-off delay of T1 is only slightly incre...