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Method for Interlacing Processor Memory Accesses to a Display Buffer With Screen Refresh Display Buffer Accesses

IP.com Disclosure Number: IPCOM000038514D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Arismendi, A: AUTHOR

Abstract

In the prior art, application programs need to monitor a status register and wait for horizontal or vertical sync dead time to update or read the display buffer. In the new method, interlacing processor accesses with the refresh accesses eliminate the memory contention which causes display static of flicker. Display adapters for cathode ray tube (CRT) monitors and television sets recommend that any updating or reading of the display buffer be done during horizontal or vertical sync dead time. This is to avoid the hashing or static that will occur due to display memory contention. Others require that the video to the display be turned off during the updates or reads. This method avoids the need to wait for horizontal or vertical syncs, but the result is a flicker of the contents on the screen.

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Method for Interlacing Processor Memory Accesses to a Display Buffer With Screen Refresh Display Buffer Accesses

In the prior art, application programs need to monitor a status register and wait for horizontal or vertical sync dead time to update or read the display buffer. In the new method, interlacing processor accesses with the refresh accesses eliminate the memory contention which causes display static of flicker. Display adapters for cathode ray tube (CRT) monitors and television sets recommend that any updating or reading of the display buffer be done during horizontal or vertical sync dead time. This is to avoid the hashing or static that will occur due to display memory contention. Others require that the video to the display be turned off during the updates or reads. This method avoids the need to wait for horizontal or vertical syncs, but the result is a flicker of the contents on the screen. Interlacing processor accesses with the screen refresh eliminates the need for application programs to monitor the horizontal or vertical sync status. The architecture of this system requires that the display controller be the sole interface to the display buffer memory, as shown in Fig. 1. Fig. 2 depicts an implementation of the interlacing scheme. It assumes alphanumeric text is being displayed. The text is defined in two bytes as a character scan code and a character attribute. A character font byte dependent on the scan code is fetched. The character attribute may then alter the font byte to generate the data sent to the display. A processor access, memory read or write, is synchronized to the display refresh states. Logic block 10 latches the processor access, and block 11 then synchronizes the access with the display controller's internal clock. Block 12 causes the +I/O channel Ready signal to become inactive to introduc...