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Method for Testing Keyboard Adapter

IP.com Disclosure Number: IPCOM000038521D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Davenport, CS: AUTHOR [+2]

Abstract

A method of testing a keyboard adapter which reduces the test time and the number of test cases is described. This method employs only one test case which simulates all the depressions of each key plus the special functions. The long count between keystrokes is eliminated for testing this adapter. In order to test a keyboard adapter, it was necessary in the prior art to bypass the long count for the noise/debounce period of 5 milliseconds (msec). To ensure that the keyboard adapter is totally operational, it was also necessary that every single key be tested and simulated extensively. In the adapter under test, all the I/O READ, WRITE, and wait signals are generated internally due to the combining of the keyboard circuitry with the system bus controller and the interrupt controller within one LSI gate array chip.

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Method for Testing Keyboard Adapter

A method of testing a keyboard adapter which reduces the test time and the number of test cases is described. This method employs only one test case which simulates all the depressions of each key plus the special functions. The long count between keystrokes is eliminated for testing this adapter. In order to test a keyboard adapter, it was necessary in the prior art to bypass the long count for the noise/debounce period of 5 milliseconds (msec). To ensure that the keyboard adapter is totally operational, it was also necessary that every single key be tested and simulated extensively.

In the adapter under test, all the I/O READ, WRITE, and wait signals are generated internally due to the combining of the keyboard circuitry with the system bus controller and the interrupt controller within one LSI gate array chip. In accordance with the new method, a software model is created to emulate the Intel 8088 processor and the bus is configured in the MAX mode to access the adapter chip. To assure minimum testing time and maximum test coverage, several AND-OR circuits were put in to allow the counters to switch from normal (5 msec) to fast (1.2 usec). The fast count bypasses the 5-msec counters using the system clock ANDed with test mode. In normal mode, the fast count is gated off. In order to guarantee that all the counter bits are operational, all the counters are synchronized with the bits being ANDed and ORed to sense all 1's and a...