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Fault-Detecting Adder

IP.com Disclosure Number: IPCOM000038532D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Woodward, SS: AUTHOR

Abstract

This concept relates to a class of binary adders consisting of a first module followed by a series of identical modules. Each module accepts one or more bits of each of the operands and delivers the corresponding number of sum bits. The last module also delivers the carry, the sum parity, and an error-indication signal. The design is such that all single stuck-at faults, which deliver a wrong output, will raise the (Image Omitted) error indication. The characteristic, unique feature of these adders is a design which adheres to a certain set of rules given below. Furthermore, there is a simple set of diagnostic inputs which can be used to detect all single stuck-at faults in the adder provided they are not masked by internal logical redundancies. The adder must be of a modular structure, as depicted in Figs. 1 and 2.

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Fault-Detecting Adder

This concept relates to a class of binary adders consisting of a first module followed by a series of identical modules. Each module accepts one or more bits of each of the operands and delivers the corresponding number of sum bits. The last module also delivers the carry, the sum parity, and an error-indication signal. The design is such that all single stuck-at faults, which deliver a wrong output, will raise the

(Image Omitted)

error indication. The characteristic, unique feature of these adders is a design which adheres to a certain set of rules given below.

Furthermore, there is a simple set of diagnostic inputs which can be used to detect all single stuck-at faults in the adder provided they are not masked by internal logical redundancies. The adder must be of a modular structure, as depicted in Figs. 1 and 2. Each module processes k bits from each of the operands a and b to produce k sum bits. The first module has four primary inputs: 1. THE FIRST K BITS OF EACH OF THE OPERANDS A AND B. 2. Redundant copies of the carry into the adder, c(0)

and c(0)r. 3. Overall parity for all of the operand bits

included in all of the modules, ac and bc. The other modules each have k bits of each of the operands for primary inputs. Primary outputs for all of the modules consist of k sum bits. The last module also has the adder carry out, the final sum parity, and the error detector indication as primary outputs. Each module, except the last, has three module outputs which serve as module inputs to the next module: 1. A module carry output c(i+1) for the (i+1)st

module. 2. A sum parity sc(i+1) accumulated over the sum bits

developed by the (i+1)st module and its predecessors. 3. An error detector line E(i+1) which will be

inverted from the error-free state if a fault is

detected in the (i+1)st module or its predecessors.

The error detector line of the last module will be in

logical 1 state if a fault is detected in any module. The module structure uses d...