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Browse Prior Art Database

HIGH Performance Word Decoder for Bipolar Ram

IP.com Disclosure Number: IPCOM000038534D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

This article describes a word line decoder/driver circuit employing the intrinsic device capacitance (diffusion capacitance) of an inverse transistor for speed enhancement. Fig. 1 shows a word line decoder/driver circuit. It includes a current switch decoder input stage and double-ended push-pull driver outputs to drive two half arrays. One limitation of this circuit is its deselection speed, which is determined by the fall time of node 1 and the active pull-up rate of the upper word line (WL). Due to the double- ended driving, node 1 is heavily loaded and its switching speed is limited by the Current Switch current. The disclosed circuit shown in Fig. 2 uses a novel capacitor speed enhancement technique to improve the time of node 1.

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HIGH Performance Word Decoder for Bipolar Ram

This article describes a word line decoder/driver circuit employing the intrinsic device capacitance (diffusion capacitance) of an inverse transistor for speed enhancement. Fig. 1 shows a word line decoder/driver circuit. It includes a current switch decoder input stage and double-ended push-pull driver outputs to drive two half arrays. One limitation of this circuit is its deselection speed, which is determined by the fall time of node 1 and the active pull-up rate of the upper word line (WL). Due to the double- ended driving, node 1 is heavily loaded and its switching speed is limited by the Current Switch current. The disclosed circuit shown in Fig. 2 uses a novel capacitor speed enhancement technique to improve the time of node 1. The two improvements of the new circuit are described as follows: 1) The reference transistor T4 in Fig. 1 is replaced by an inverse base-collector diode. The inherent junction capacitance Ccb, Ccs and Cbe of this device are employed for speed enhancement. In the

(Image Omitted)

circuit shown in Fig. 2, the capacitive effect seen by node 2 is formulated as: a) Input is HIGH ( T1 ON and T4 OFF ) (Unselect state)

C N Ccs (T4) + Ccb (Depletion) (T4)

b) Input is DOWN (T1 OFF and T4 ON ) (Select state)

C N Ccs (T4) + Ccb (Depletion + Diffusion)(T4) + Cbe (T4)

The large diffusion capacitance of T4 is employed to provide the high transient current drive needed to pull down node 1 rapidly when T...