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QUARTER VDD SENSING SCHEME IN CMOS DRAM

IP.com Disclosure Number: IPCOM000038539D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Chin, D: AUTHOR [+2]

Abstract

This article describes a new sensing scheme with a quarter VDD precharge method whose access time can be much faster than half VDD sensing in a high performance CMOS DRAM (complementary metal-oxide-semiconductor dynamic random-access memory) design. The quarter VDD sensing (QVS) is so-called because bitlines are precharged to VDD-VTN, in which VTN is the threshold voltage of an NMOS transistor and is close to a quarter of VDD. This new sensing technique will be useful in designing even faster CMOS DRAM circuits. Fig. 1 shows the circuit diagram for scheme, where NMOS transistors Q1 and Q2 precharge the bitlines (BL and BLN) to VDD-VTN when PEQ is high at VDD for a p-channel array. Q3 further equalizes the bitline potential. It should be noted that removal of Q1 and Q2 would result in conventional half VDD sensing (HVS). Fig.

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QUARTER VDD SENSING SCHEME IN CMOS DRAM

This article describes a new sensing scheme with a quarter VDD precharge method whose access time can be much faster than half VDD sensing in a high performance CMOS DRAM (complementary metal-oxide-semiconductor dynamic random-access memory) design. The quarter VDD sensing (QVS) is so-called because bitlines are precharged to VDD-VTN, in which VTN is the threshold voltage of an NMOS transistor and is close to a quarter of VDD. This new sensing technique will be useful in designing even faster CMOS DRAM circuits. Fig. 1 shows the circuit diagram for scheme, where NMOS transistors Q1 and Q2 precharge the bitlines (BL and BLN) to VDD-VTN when PEQ is high at VDD for a p-channel array. Q3 further equalizes the bitline potential. It should be noted that removal of Q1 and Q2 would result in conventional half VDD sensing (HVS). Fig. 2 shows half VDD sensing (HVS), and Fig. 3 shows quarter VDD sensing (QVS).

With an unboosted wordline, the voltage conditions are as shown in the table for QVS and HVS. where VTP is the threshold of the P-channel device without substrate effect and VTN is the N-channel substrate threshold augmented by substrate effect (source above ground). The charging (rising) transient on the storage node when reading a stored zero is faster in QVS for two reasons: 1) As the selected word line drops, the transfer device turns earlier (at VDD -VTN - VTP for QVS vs VDD/2 - VTP for HVS); 2) the final gate drive on the...