Browse Prior Art Database

Storage Address Generator

IP.com Disclosure Number: IPCOM000038540D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Wicker, CR: AUTHOR

Abstract

This article describes a circuit arrangement in which memory locations can be addressed without the use of address decoders, etc. The circuit arrangement includes a shift register/memory module. A single bit is fed back from the memory module and is used for generating the next address. Sometimes there is a need to access basic information that does not change. Generally, that information is considered to be part of a memory address space and is accessed the same as any other memory data. Usually, an address decoder must be used to decode the address. Also, if the memory is connected to a multiplexer bus, address latches are required. The figure shows a circuit configuration for accessing the same basic information without using storage address spaces.

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Storage Address Generator

This article describes a circuit arrangement in which memory locations can be addressed without the use of address decoders, etc. The circuit arrangement includes a shift register/memory module. A single bit is fed back from the memory module and is used for generating the next address. Sometimes there is a need to access basic information that does not change. Generally, that information is considered to be part of a memory address space and is accessed the same as any other memory data. Usually, an address decoder must be used to decode the address. Also, if the memory is connected to a multiplexer bus, address latches are required. The figure shows a circuit configuration for accessing the same basic information without using storage address spaces. The outputs from a shift register module are connected to the inputs of a storage module, such as a PROM, RAM, ROS, EPROM, EEPROM, etc. The storage module must be at least one bit wider than the width of a desired data fetch. The extra bit is used as the input to the shift register that generates the next address to the storage module. The binary value of this feedback bit is specified so that when shifted into the shift register, a new address is generated. Because there are multiple codings for the memory map using the extra bit, all addresses of the storage will be accessed without repeating any address. The addresses are generated nonsequentially so the data is stored according to the...