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Address Multiplexing to Support Different Size Dynamic RAM Modules

IP.com Disclosure Number: IPCOM000038558D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Corkell, AF: AUTHOR [+3]

Abstract

This article describes a technique of multiplexing address lines into dynamic random-access memory (RAM) chips to support different-size modules. Dynamic RAM chips generally are made in families. All members of a particular family have compatible timings and pin outs. The only difference between members of a family is the number of bits of storage that the chip has and consequently the number of address lines required to address all those bits. Currently dynamic RAM chips come in families with three different sizes of chips. These chips are 16K x 1, 64K x 1, and 256K x 1 which take 14, 16, and 18 bits of address, respectively, to access all the data in the RAM chip.

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Address Multiplexing to Support Different Size Dynamic RAM Modules

This article describes a technique of multiplexing address lines into dynamic random-access memory (RAM) chips to support different-size modules. Dynamic RAM chips generally are made in families. All members of a particular family have compatible timings and pin outs. The only difference between members of a family is the number of bits of storage that the chip has and consequently the number of address lines required to address all those bits. Currently dynamic RAM chips come in families with three different sizes of chips. These chips are 16K x 1, 64K x 1, and 256K x 1 which take 14, 16, and 18 bits of address, respectively, to access all the data in the RAM chip. To reduce pin count on the package, the chips are designed with a multiplexed addressing scheme which cuts in half the number of address lines that go into the chip. The RAM chips have 7, 8 and 9 address lines, respectively. This multiplexing scheme is implemented with two control lines: row address strobe (RAS) and column address strobe (CAS). The first half of the address is activated, and then RAS is asserted. Then the second half of the address is put on the address lines and CAS is asserted. Thus the whole address gets into the dynamic RAM chip. Since the memory chips come in different sizes and since different users of a product may desire different amounts of memory on that product, it is desirable to have a system that will be able to use all the differe...