Browse Prior Art Database

Polycrystalline Silicon Contact to the High Barrier SBD

IP.com Disclosure Number: IPCOM000038564D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Wheeler, DC: AUTHOR

Abstract

Disclosed is a method of making Schottky barrier diodes (SBDs) with P+ guard rings that may be wired up at the N+ polysilicon layer used for the emitter in semiconductor devices. This makes it possible to free up some wiring channels at the first level metal for other purposes. An enhancement of the method also makes it possible to short the junction between P+ polysilicon and N+ polysilicon layers with a self- aligned silicide strap. (Image Omitted) In the process, existing lithography and reactive ion etch are used on a previous photolevel (L1) to define the anode through the SiO2/Si3N4 stack 2 (Fig. 1). Polysilicon-emitter lithography (level L2) is used on the photoresist 1 to define the annular ring of N+ polysilicon 3. The overetch of level L2 (Fig.

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Polycrystalline Silicon Contact to the High Barrier SBD

Disclosed is a method of making Schottky barrier diodes (SBDs) with P+ guard rings that may be wired up at the N+ polysilicon layer used for the emitter in semiconductor devices. This makes it possible to free up some wiring channels at the first level metal for other purposes. An enhancement of the method also makes it possible to short the junction between P+ polysilicon and N+ polysilicon layers with a self- aligned silicide strap.

(Image Omitted)

In the process, existing lithography and reactive ion etch are used on a previous photolevel (L1) to define the anode through the SiO2/Si3N4 stack 2 (Fig. 1). Polysilicon-emitter lithography (level L2) is used on the photoresist 1 to define the annular ring of N+ polysilicon 3. The overetch of level L2 (Fig. 2) is used to recess the anode surface below the P+ region 4 exposing the N-type epitaxial silicon 5. Annealing of the emitter is next done, and then self-aligned silicide 6 is formed to complete the SBD. It is also possible to strap two different level layers of P-type polysilicon 7 and N-type silicon 3 (Fig. 3). The need for J-stud and first metal may be eliminated in the clamped NPN insofar as integrating the SBD with the transistor.

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