Browse Prior Art Database

64k Static RAM Word and Bit Decoder Circuit

IP.com Disclosure Number: IPCOM000038568D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Mao, RS: AUTHOR

Abstract

A word line decoding technique has been developed which uses a dynamic circuit in an asynchronous operation environment to improve speed and power. Circuitry has also been proposed to use the bit decoder in RAM (random-access memory) systems to provide a bit line precharge circuit and bit line preamplification which will improve decoder noise tolerance. The development combines a conventional decoder with a standard clock drive in order to provide good driving capability to the word line. The SUBFET word decoder is shown in Fig. 1, and the timing diagram in Fig. 2. The RLD clock precharges the selected section of the word decoders.

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64k Static RAM Word and Bit Decoder Circuit

A word line decoding technique has been developed which uses a dynamic circuit in an asynchronous operation environment to improve speed and power. Circuitry has also been proposed to use the bit decoder in RAM (random-access memory) systems to provide a bit line precharge circuit and bit line preamplification which will improve decoder noise tolerance. The development combines a conventional decoder with a standard clock drive in order to provide good driving capability to the word line. The SUBFET word decoder is shown in Fig. 1, and the timing diagram in Fig. 2. The RLD clock precharges the selected section of the word decoders. The internal node of the selected decoder follows the precharge clock while the internal node of the unselected decoder will be clamped below the threshold voltage of the Schmitt trigger delay stage by the true-complement address lines. The Schmitt trigger delay stage guarantees a minimum bootstrap level for the selected decoder while providing sufficient noise margin for the unselected one. This is because it was designed with a high threshold. The word decoder precharge device is much larger than those in the conventional, as well as the clocked, static RAM. It precharges the bootstrap node much faster so as to improve access time. It actively holds the precharged pocket against surges or upsets on the address lines until the word line rises.

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Under certain conditions large upsets at the proper time may still damage the bootstrapped level and weaken the word line up level. In such instances the error is limited to one data access. During skewed input conditions the RLD clock will stay high until the selected word line rises. The misfired decoder will discharge its bootstrap node and turn off the word line.

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The RDE1 and RDE2 clocks will select either the left side or the right side of the word line to reduce active power consumption. The decoder precharge clock turns off immediately after the word line rise to also improve the active power. After the data access the I/O latch set clock disables the s...