Browse Prior Art Database

Self-Aligned Dynamic RAM

IP.com Disclosure Number: IPCOM000038570D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Goth, GR: AUTHOR [+2]

Abstract

A dynamic random-access memory (RAM) cell with high density and performance has been developed which may be used in polyimide-filled trench (PIT) and other semiconductor devices. The development centers around the presence of a compact, high capacity, low leakage storage capacitor that is incorporated into a single bipolar memory cell. In semiconductors, dynamic memory cells must have very low leakage in the storage node, even at elevated temperatures, and also have a large capacitance in the storage node. These requirements tend to be mutually exclusive if the data is stored in one of the P-N junctions of the device. The memory cell proposed resolves this problem by storing the data in a capacitor formed between the single crystal silicon and a thin layer of polysilicon with a thin thermal oxide layer separating them.

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Self-Aligned Dynamic RAM

A dynamic random-access memory (RAM) cell with high density and performance has been developed which may be used in polyimide-filled trench (PIT) and other semiconductor devices. The development centers around the presence of a compact, high capacity, low leakage storage capacitor that is incorporated into a single bipolar memory cell. In semiconductors, dynamic memory cells must have very low leakage in the storage node, even at elevated temperatures, and also have a large capacitance in the storage node. These requirements tend to be mutually exclusive if the data is stored in one of the P-N junctions of the device. The memory cell proposed resolves this problem by storing the data in a capacitor formed between the single crystal silicon and a thin layer of polysilicon with a thin thermal oxide layer separating them. As indicated in Fig. 1, the cell consists of a large capacitor attached to the floating subcollector of the NPN device. The base is connected to the word line, and the emitter is connected to the bit line. The polysilicon, which serves as the other plate of the storage capacitor, can be tied to any fixed potential, such as the Vcc supply, or it may be switched to boost the stored charge. The layout of the cell in Fig. 2 shows base 1 connected to word line 2 (first level metal) and emitter 3 connected to bit line 4 on the

(Image Omitted)

second level metal. The PolySi 5 is wrapped around the periphery of the device as a coat...