Browse Prior Art Database

Expand Memory Addressing Capability of 16-Bit Microprocessor

IP.com Disclosure Number: IPCOM000038575D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Heisey, RE: AUTHOR [+3]

Abstract

The memory addressing capability of a 16-bit microprocessor is inherently limited to 64K. Various schemes have been devised to exceed this natural limit. One known device permits addressing 512K memory. The present embodiment, applied to that device, expands the limit from 512K to 896K, and provides increased reliability and flexibility. Referring to the figure, it is seen that the 512K base memory 1 is fully addressable by known device 2 which generates the necessary 20- bit memory addresses. The figure also shows that, for the present embodiment, the base memory is supplemented by memory extension 3 and shadow (back-up) memory 4. It is further seen that these two 384K supplements are associated with the upper 384K of base memory 1.

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Expand Memory Addressing Capability of 16-Bit Microprocessor

The memory addressing capability of a 16-bit microprocessor is inherently limited to 64K. Various schemes have been devised to exceed this natural limit. One known device permits addressing 512K memory. The present embodiment, applied to that device, expands the limit from 512K to 896K, and provides increased reliability and flexibility. Referring to the figure, it is seen that the 512K base memory 1 is fully addressable by known device 2 which generates the necessary 20- bit memory addresses. The figure also shows that, for the present embodiment, the base memory is supplemented by memory extension 3 and shadow (back-up) memory 4. It is further seen that these two 384K supplements are associated with the upper 384K of base memory 1. The figure also shows the addition of program-controlled I-fetch line 5, which provides the additional bit 21 required for memory addresses of 512K and above, and four program controlled memory operation code latches 6 (C-1, C-2, C-4, C-8). Line 5 together with latches C-1 and C-2 permit flexibility in addressing Hi-memory (512-896) or Lo-memory (128-511) for I-fetches and Data-fetches, as follows: If: No I-fetch and C-1 = 1 then Data Hi

No I-fetch and C-1 = 0 then Data Lo

I-fetch and C-2 = 1 then Instr Hi

I-fetch and C-2 = 0 then Instr Lo When latch C-1 = 0, latches C-4 and C-8 permit additional memory flexibility in handling data, as follows: If: C-4 = 0 Data-fetches are from Lo-memory 128-511K.

C-4 = 1 Data-fetches are from shadow memory 128-511K.

C-8 = 0 Data written to addresses 128-511K writes in both

Lo-memory and shadow memory.

C-8 = 1 and C-4 = 0 Data writes in Lo-memory only.

C-8 = 1 and C-4 = 1 Data writes in shadow memory only. Normally C-1 = 0, C-2 = 1, C-4 = 0, and C-8 = 0. Therefore, Data- fetches are from Lo-memory addresses 128-511K, I-fetches are from Hi- memory address...